1. Field of the Invention
The present invention relates to semiconductor structures and methods of forming the semiconductor structures, and more particularly to bonding structures and methods of forming bonding structures.
2. Description of the Related Art
With advances associated with electronic products, semiconductor technology has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emission diodes (LEDs), laser diodes and other devices or chipsets. In order to achieve high-integration and high-speed goals, dimensions of semiconductor integrated circuits continue to shrink. Various materials and techniques have been proposed to achieve these integration and speed goals and to overcome manufacturing obstacles associated therewith. In order to shrink die size, a through wafer via (TWV) technique has been used in this field.
FIGS. 1A-1E are cross-sectional views showing a prior art method of forming TWV.
As shown in FIG. 1A, a multi-level interconnect structure 110 comprising metal layers 115 is formed over a substrate 100. Bonding pads 125 are formed over the multi-level interconnect structure 110. A passivation layer 120 is formed over the bonding pads 125 and includes openings 130 formed therein partially exposing the bonding pads 125.
In FIG. 1B, a dummy substrate 150 is bonded on the passivation layer 120 by a thermal tape 155. The dummy substrate 150 serves as a carrier for grinding the substrate 100. After the thermal tape bonding, the substrate 100 is grinded, thereby forming a remaining substrate 100a having a thickness of about 150 μm as shown in FIG. 1C.
Turning to FIG. 1D, TWVs 160 are formed within the substrate 100a, contacting with the metal layers 115. TWVs 160 provide electrical connection between the metal layers 115 to which diodes or circuits are coupled and another substrate (not shown). TWVs 160 usually include a diffusion barrier layer and a metal layer which is formed by a chemical vapor deposition (CVD) or physical vapor deposition (PVD) step having a processing temperature of about 300° C. The diffusion barrier layer can be a conductive layer such as a metal nitride layer or a dielectric layer such as a silicon nitride layer. The thermal tape 155, however, cannot tolerate such a processing temperature, and the thermal tape 155 may dissolve and/or fail to adequately bond the dummy structure 150 to the passivation layer 120. The dummy substrate 150 may separate from the passivation layer 120 in subsequent processing steps, such as a chemical mechanical planarization (CMP) processing step for planarizing the metal layer provided for the formation of the TWVs 160. Consequently, the substrate 100a can be damaged by the CMP step.
From the foregoing, semiconductor structures and methods of forming the semiconductor structures are desired.